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this is information on a product in full production. november 2015 docid027845 rev 2 1/18 sclt3-8bq7 high speed digital input current limiter with digital filter datasheet - production data features ? 8 inputs - 8-bit spi output ? high side input with common ground ? 5 v voltage regulator ? package: qfn 7x7 - 48l ? 30 v reverse polarity capable ? adjustable current limiters ? led output for visual status ? optional: 16-bit mode with parity check, temperature and voltage alarms ? daisy chain capable ? input digital filter with adjustable delay: 20 s to 3 ms ? power dissipation: 78 mw per channel complies with following standards: ? iec61000-4-2: ? 8 kv contact discharge ? 15 kv air discharge ? iec61000-4-4: ?4 kv ? iec61000-4-5: ? input: 1 kv ? power supply: 2.5 kv application ? programmable logic controller and remote input modules ? high speed protected termination for digital input with serialized spi output ? iec61131-2 type 1, 2 and 3 ? compliant with en60947-5-2 benefits ? simplified design due to ? built-in over voltage robustness and immune data transfer ? compliance with sensors and plc's standards ? space saving in cost effective solution with ? integrated qfn 7x7 package ? spi output reducing opto-couplers quantity ? energy efficient solution ? energy-less input led visual status powered by inputs current ? low overall dissipation versus discrete description the sclt3-8bq7 provides an 8-line protected digital input termination with serialized state transfer. this device enhances the i/o module density by cutting the dissipation (78 mw per input) and reducing the count of opto-transistors. an adjustable digital filter and an led driver are embedded in each type 3 input section. its 2 mhz spi peripheral output serializes the input state transfer to the i/o module controller. 4)1[/ 7239,(: %277209,(: www.st.com
circuit block diagram sclt3-8bq7 2/18 docid027845 rev 2 1 circuit block diagram figure 1. circuit block diagram figure 2. basic application schematic ,1 &20 3 /' ,1 , /' , '95 5() 26& &20 6 9 '' 9 &6 &6 630 9 & 6&. 0,62 0,62 026, 026, 6+,)7 elw 9 '' 6+,)7 &$3785( 9 5 3urwhfwhglqsxw 3urwhfwhglqsxw 9 ,1 9 5 , w r 9 '' 9 '' &20 9 '' 9 &6 &6 630 9 & 6&. 0,62 0,62 026, 9 '' :5,7( &xuuhqw uhihuhqfh 2vfloodwru &orfnglylghu ?vpvgljlwdoilowhu v olqhv olqhv olqhv olqhv olqhv ,qsxwvwdwhuhjlvwhu 'dwdvwdwhuhjlvwhu &rqwurovwdwhuhjlvwhu 7udqvihu orjlf 3rzhu uhvhw 3rzhu vxsso\ 3dulw\ elwvjhq 2yhuwhpshudwxuh dodup 8qghuyrowdjh dodup 9 '' 9 '' '95 630 26& &20 3 &6 6&. 0,62 5() 5 5() 5 & 9 &6 9 & ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 5 6 5 3' 5 , 5 , 5 , 5 , 5 , 5 , 5 , 5 , /(' /(' /(' /(' /(' /(' /(' /(' &20 6 9 && &20 3 9 , 9 , 9 , 9 , 9 , 9 , 9 , 9 , 026, &20 3 5 26& $&3/ ./ $&3/ :/ 0,62
docid027845 rev 2 3/18 sclt3-8bq7 circuit block diagram 18 1.1 i/o pin description table 1. i/o pin descriptions name type description pin # in i power input logic input with current limitation, i = 1 to 8 16, 17, 18, 19, 21, 22, 23, 24 ld i power output led output driver with current regulation, i = 1 to 8 34, 35, 36, 37, 38, 39, 40, 41 v c power input 24 v sensor power supply 13 v cs signal input 24 v sensor power supply sensing input 14 com p ground power ground of power sensor supply 7, 15, 20, 31 v dd power output 5 v logic power supply 1 com s ground signal ground of logic / output section 43 ref signal input input current limiter reference setting 42 spm signal input spi shift register length selector -spm to gnd --> 16 bits -spm to vdd --> 8 bits 4 /cs logic input spi chip select signal 48 sck logic input spi serial clock signal 47 mosi logic input spi serial data input signal 46 dvr logic input divider ratio selector of the digital input filters (8 or 64 steps) 2 osc signal input delay setting of the digital input filters 3 miso logic output spi serial data output signal 44 /miso logic output inverting spi serial data output signal 45 tab substrate exposed pad: connected to die substrate, to be connected to com p tab nc not connected (or to be connected to com p ) 5, 6, 8, 9, 10, 11, 12, 25, 26, 27, 28, 29, 30, 32, 33
circuit block diagram sclt3-8bq7 4/18 docid027845 rev 2 figure 3. pinout description of the qfn7x7-48l version (top view) the package is the qfn7x7-48l exposed pad that improves ground cooling transfer of input dissipation to the printed board. figure 4. basic module input characteristics in type 3 '95 630 &20 3 9 '' 9 &6 &20 3 ,1 ,1 ,1 ,1 &20 3 ,1 ,1 ,1 ,1 9 & /(' &20 3 /(' /(' &6 6&. 026, 0,62 &20 6 5() /(' /(' /(' /(' /(' 0,62 26& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 7$% v i (v) 0 5 10 15 20 25 30 0 0.5 1 1.5 2 3 i in (ma) 2.1ma 2.6ma on off 11v r i = 2.2 k v i =v in + r i x i in r i sclt r i sclt 2.5
docid027845 rev 2 5/18 sclt3-8bq7 characteristic information 18 2 characteristic information table 2. absolute maximum ratings symbol pin parameter name conditions value unit v cc v c bus power supply dc voltage 500 ? < r c < 2.2 k ? -0.3 to 35 v v c v c sclt3-8bq7 power supply voltage r c = 0 k ? -0.3 to 30 v i cc v c maximum bus power supply current 15 ma v cs v cs sensing bus power supply voltage -0.3 to 6 v i dd v dd maximum output power supply current r c = 500 ? 12 ma v i in i input steady state voltage, i = 1 to 8 r i = 2.2 k ? -30 to 35 v i in in i input forward current range -20 to 10 ma i osc osc maximum sourced oscillator current 120 a lv i sck /cs mosi logic input voltage -0.3 to 6 v t stg all storage temperature range -40 to 150 c t amb ambient temperature range -40 to 105 c
characteristic information sclt3-8bq7 6/18 docid027845 rev 2 table 3. operating conditions symbol pin parameter name conditions value unit v cc v c bus power supply steady state voltage r c > 500 ? 15 to 35 (1) v v dd v dd internal logic power supply voltage 5 v i dd v dd internal logic power supply voltage r c > 500 ? 10 ma v i in input repetitive steady state voltage r i = 2.2 k ? (2) -30 to 35 v v ld ld i maximum led output voltage, i = 1 to 8 2.7 v f in max in maximum single input frequency 8-bit mode 20 khz f sck max maximum spi clock frequency 0.1 to 2 mhz r osc osc filter oscillator resistance range 15 k to 1.5 m ? lv sck /cs mosi miso /miso logic input/output voltages 0 to 5.5 v t amb all operating ambient temperature range v cc 30 v -40 to 85 c v cc 24 v r th(j-a) = 70 c/w -40 to 105 c t j operating junction temperature range -40 to 150 c 1. 32 v in dc; 35v during 0.5 s max 2. v i = v in + r i x i in table 4. dc electrical characteristics based on figure 2 application environment symbol pin name conditions min. typ. max. unit input current limitation i lim in input limiting current v in = 5.5 to 26 v r i = 2.2 k ? 2.1 2.35 2.6 ma i on ld i on state led current v i = 11 v 2 ma input digital filter t osc osc oscillator period r osc = 51 k ? 1.13 1.37 s r osc = 1200 k ? 20 28 s r osc osc oscillator resistance 51 1200 k ? t ckf ckf period dvr = v dd 64 x t osc dvr = com s 8 x t osc t ft in filtering time 2 x t ckf 3 x t ckf
docid027845 rev 2 7/18 sclt3-8bq7 characteristic information 18 figure 5. time diagram table 5. spi electrical characteristics (t j = 25 c, v cc = 24 v, v dd = 5 v respect to com ground pin; unless otherwise specified) symbol pin name conditions min. typ. max. unit f ck sck clock frequency 2 mhz t s mosi data setup time mosi toggling to sck rising 25 ns t d miso write out propagation time sck falling to miso toggling, c out = 10 pf 50 ns t ld sck enable lead time /cs falling to sck rising 80 ns t hc sck clock hold time sck falling to /cs rising 160 ns t dt /cs transfer delay time /cs rising to /cs falling 150 ns t h mosi data hold time sck rising to mosi toggling 25 ns t dis miso data output disable time /cs rising to miso disabled 200 ns lv ih mosi sck /cs logic input high voltage share of v dd 70 % lv il logic input low voltage share of v dd 30 % lv oh /miso miso logic output high voltage i oh = 3ma 4 4.75 v lv ol logic output low voltage i ol = 3ma 0.25 1 v t ro , t fo miso /miso miso signal fall/rise time i miso = 3ma 20 ns t a miso output access time /cs falling to miso toggling 40 80 ns ducy sck clock duty cycle 25 75 % 0,62 026, 6&. &6 06% 0 06% 6 7 $ 7 /' 7 6 7 &+ 7 + 7 ' /6% 0 /6% 6 06% 0 06% 6 7 ',6 7 +& 7 ) 7 5 7 '7 7 &/ 7 )5$0(
characteristic information sclt3-8bq7 8/18 docid027845 rev 2 table 6. electromagnetic compatibility ratings symbol pin parameter name (1) value unit v ppb v i peak pulse voltage burst, iec61000-4-4 (2) 4kv v pp v i peak pulse voltage surge, iec61000-4-5 1 kv v pp v cc peak pulse voltage surge, iec61000-4-5 2.5 kv v esd v in esd protection, iec 61000-4-2, per input ?air ? contact 15 8 kv 1. test set-up, see application figure 2 . 2. see an3031.
docid027845 rev 2 9/18 sclt3-8bq7 functional description 18 3 functional description 3.1 operation of the sclt3-8bq7 with the spi bus (c pol = 0, c pha = 0) the spi bus master controller manages the data transfer with the chip select signal /cs and controls the data shift in the register with the clock sck signal. figure 6. serial data format frame the transfer of the sclt3-8bq7 input states in the spi registers starts when the chip select /cs signal falls and ends when this /cs is rising back. the transfer of data out of the sclt3-8bq7 slave miso output starts immediately when the chip select /cs goes low. then, the input mosi is captured and presented to the shift register on each rising edge of the clock sck. and the data are shifted in this register on each falling edge of the serial clock sck, the data bits being written on the output miso with the most significant bit first. 3.1.1 the serial data input mosi this input signal mosi is used to shift external data bits into the sclt3-8bq7 register from the most significant msb bit to the lower significant one lsb. the data bits are captured by the sclt3-8bq7 on the rising edge of the serial clock signal sck. 3.2 the input digital filter depending on the biasing of the spm pin, the data frame is 8-bits or 16-bits. a digital filter is implemented between the input state comparator and the input state register. it consists of a 2-step sampling circuit that is controlled by an oscillator as shown on figure 7 . the filtering time t ft is set by the external oscillator resistor and is a function of the oscillator period t ckf : ? 2 x t ckf < t ft < 3 x t ckf ? t ckf = divider ratio x t osc (r osc ) 06% 0 06% 6 /6% 0 /6% 6 06% 0 06% 6 0,62 026, 6&. &6 '$7$&$3785(
functional description sclt3-8bq7 10/18 docid027845 rev 2 this period can be adjusted between 20 s and 3000 s as shown on table 7 . being placed in the front end of the module, this filter increases the transient immunity of the sclt and its spi logic circuitry. it also simplifies the input management software task of the asic controller. figure 7. two step digital filter placed after the analog section of the logic input 3.3 the spi data transfer operation 3.3.1 the spi data frame depending on the biasing of the spm pin, the data frame is 8-bits or 16-bits. the selected structure of the spi is a 16-bit word in order to be able to implement the input state data and some control bits such as the uva alarm, the 4 checksum bits and the two low & high state stop bits. table 7. typical setting of the digital filter timings input speed fast medium slow input frequency (khz) 60 20 5 0.3 min. filter time t ft (s) 20 50 230 3000 osc resistance (k ? ) 51 150 82 1300 ckf period t ckf (s) 10 25 115 1500 dvr connection com s com s v dd v dd divider ratio 8 8 64 64 '4 4 &. '4 4 &. 4 6 5 &.) ,1 287 '4 4 &. &.) ,1 287 7
docid027845 rev 2 11/18 sclt3-8bq7 functional description 18 3.3.2 the spi data transfer the sclt3-8bq7 transfers its 16 data bits through the spi within one chip select hi-lo-hi sequence. so, this length defines the minimum length that the shift register of the spi master controller is able to capture: 16 bits. the ta b le 8 shows the 16-bit mode way the data are transferred starting from the data bits, the control bits and ending by a stop bit. 3.4 control bit signals of the spi transferred data frame 3.4.1 the power bus voltage monitoring the uva circuit generates the alarm /uva that is active low when the power bus voltage is lower than the activation threshold v con , 17 v typical, and it is disabled high when the power bus voltage rises above the threshold v coff , 18 v typical. 3.4.2 the over temperature alarm the alarm signal /ota is enabled, low state active, when the junction temperature is higher than the activation threshold t on , 150 oc typical, and it is disabled when the junction temperature falls below the threshold t off , 140oc typical. table 8. spi data transfer organization versus clt input states with spm = 0 bit # lsb bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 control high low pc4 pc3 pc2 pc1 /ota /uva last out bit # bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 msb data in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 first out
functional description sclt3-8bq7 12/18 docid027845 rev 2 3.4.3 the parity checksum bits calculation and transfer the aim of the parity checksum bit is to detect one error in the transferred spi word. several parity checksum bits are generated and transmitted through the spi on the control bit #2 to #5. in order to calculate parity bit, ?exclusive nor? operations are performed as follow: table 9. sclt3-8bq7 parity bit calculation example 3.5 loss of v cc power supply the operation of the sclt3-8bq7 is extended below the levels required in the iec 61131-2 standard to allow the implementation of the under voltage alarm uva as described the spi control bit section. if there is no more power feeding on the v cc input, the sclt3-8bq7 chip goes to sleep mode, and the miso output is forced in low state during spi transfer attempt. the last spi control data bit is a stop bit placed normally in high state all time: the loss of power supply is detected by checking its state: if low, the output is disabled by the internal power reset por. this por signal is active in low state when v c is less than 9v or the internal power supply v dd is less than 3.25 v. in8in7in6in5in4in3in2in1 10011001 pc1 pc2 pc3 pc4 1111 table 10. logic state of the spi output versus the power loss signal por and the spi chip select /cs por /cs miso /miso spi status 1 1 z z normal with no communication 1 0 1 0 normal with communication 1 0 0 1 normal with communication 0 1 z z power loss with no communication 0 0 0 1 power loss with communication attempt
docid027845 rev 2 13/18 sclt3-8bq7 functional description 18 figure 8. logic status of the sclt3-8bq7 power supply figure 9. typical limiting current i lim versus reference resistance r ref figure 10. typical limiting current i lim versus junction temperature t j 89$ 325 0,62 9 & 9 && 5 & [, & , '' 3rzhujrrg 89$odup /rvvrisr zhu 3rzhuvxsso \vwdwxv ,1 $6,& 0,62qrqlqyhu wlqjlvrodwru 9 & ,(&oh yho 9 9 9 a9 9 && 9 9 9 &6 /r 9 & 9 && 5 & [, & , '' 3rzhujrrg 89$odup /rvvrisrzhu 3rzhuvxsso\vwdwxv &6 /r &6 /r , /,0 p$ 5 5() n : 9 && 99 , 9 , /,0 p$ 7 - ?& 5 uhi n zlwk5 ,1 n 9 , wr99 && wr9
functional description sclt3-8bq7 14/18 docid027845 rev 2 figure 11. relative variation of minimum filter time t ft versus junction temperature t j figure 12. variation of junction to ambient thermal resistance r th(j-a) versus printed circuit board copper surface scu 7 )70,1 7 )70,1 ?& 7 - ?& 5 26& 0? 5 26& n? 5 wkmd ?&: 6 &8 ppe 3ulqwhgflufxlwerdug )5hsr[\ vlqjohod\hu frsshuwklfnqhvv ?p
docid027845 rev 2 15/18 sclt3-8bq7 package information 18 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 qfn7x7-48l package information figure 13. qfn7x7-48l package outline $ $ $ ' ggg & & h ' 3,1 h ( . / ' e e ( 5pqwjfx #puupnwjfx
package information sclt3-8bq7 16/18 docid027845 rev 2 table 11. qfn7x7-48l package mechanical data ref. dimensions millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min. typ. max. min. typ. max. a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.02 0.05 0.0008 0.0020 a3 0.203 0.008 b 0.18 0.25 0.30 0.0071 0.0100 0.0118 d7.00 0.275 e7.00 0.275 e0.50 0.019 d2 5.00 5.15 5.25 0.197 0.203 0.206 e2 5.00 5.15 5.25 0.197 0.203 0.206 k 0.20 0.008 l 0.30 0.40 0.50 0.011 0.015 0.019
docid027845 rev 2 17/18 sclt3-8bq7 ordering information 18 5 ordering information figure 14. ordering information scheme 6 revision history table 12. ordering information order code marking package weight base qty delivery mode SCLT3-8BQ7-TR sclt3-8bq7 qfn7x7-48l 114 mg 2500 tape and reel 6huldofxuuhqwolplwhuwhuplqdwlrq p$fxuuhqwvhwwlqj hljkwfkdqqhov %(0&ohyho n9dffruglqj wr,(& 44)1 /[ 6& /7 %4 table 13. document revision history date revision changes 29-july-2015 1 initial release. 12-nov-2015 2 updated table 4 .
sclt3-8bq7 18/18 docid027845 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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